Performance incrementers are often used to track internal operation of an integrated circuit chip to determine its performance. FIG. 1 is a diagram of a prior art performance incrementer 10, used to count and maintain a running total of various events within a circuit. Performance incrementer 10 includes a multiplexer 14 that receives on lines 16 a plurality of performance events from various locations within a circuit to be monitored. A mode select line 15 determines which of the performance events are transmitted to performance incrementer 10 through multiplexer 14. The transmitted performance event is input to a control line 20 for a multiplexer 12 for use incrementing a value within a register 11.
In particular, multiplexer 12 receives as inputs the value of register 11 on line 18 and an incremented value through incrementer logic 13 on line 17. Therefore, when the signal selected_event_increment on line 20 is high (logic “one”), multiplexer 12 transmits the signal on line 17 through to register 11. The input on line 17 is equal to the output of register 11 incremented by one through incrementer logic 13. The output of register 11 on line 19 thus represents a performance incrementer final value. This value is equal to a running total of the number of performance events that have occurred as detected through multiplexer 14.
A common performance metric that can be tracked using performance incrementer 10 includes bandwidths. Typically, for a metric such as bandwidth, performance incrementer 10 increments on each cycle for detecting a first-in-first-out (FIFO) buffer pushing or popping an entry, or detecting a bus having valid data through the performance event signals input to multiplexer 14.
It is also desirable to track latencies within a circuit. However, latencies tend to be more difficult to monitor and usually require higher level software algorithms to infer the latencies based on the bandwidths attained. Use of software results in a higher level of abstraction in performance analysis, and thus it is usually not possible to determine precise latencies within a chip using software algorithms. Furthermore, latency varies for each transaction flowing through a system.
Therefore, in order to track the latency of all transactions in a particular “snapshot” of time, a separate performance incrementer is needed for each transaction. Most systems can have thousands or even millions of transactions in the duration of time during which latencies are desired to be measured, making it infeasible to include enough performance incrementers to track them all. Also, traditional performance incrementer 10 typically cannot track other types of performance metrics such as average depth in FIFOs or flow control credits, or an average number of cache entries used.
Accordingly, a need exists for a circuit which provides for more versatility in tracking the occurrence of various performance events within a circuit.